UVM Architecture Overview

In this section we will make a quick overview of the verification
language Vlang. We will talk about the core concepts and the broad
architecture of the language.

Vlang is built on top of the D Programming Language
(Why D?). At the core of Vlang is a system specification
language called Electronic System Description Language (ESDL). ESDL is
much like SystemC, but is written from scratch in D Language and has
many improvisations including ability to run simulation on a multicore

is a Discrete Event Simulator
and the associated constructs. Vlang also defines hardware data types
that make it convenient for the verification engineer to model
bit/logic vectors and signals. Also included in the core is a BDD
based constraint solver and a glue library that allows constraints to
be declared as part of a data transaction object. On top of the core
layer, Vlang implements a port of the Universal Verification
Methodology (UVM).

The different hardware modeling verification constructs implemented by
Vlang is discussed conceptually in the following individual chapters
of the docs.