With limited on-chip RAM shared by all the processor cores, running multiple simulations on a server powered by multicore processors is no longer an optimal solution. The only way forward is to simulate using multicore enabled simulators built on shared memory software architecture.
When you code using SystemVerilog, each integral variable and any expression that you declare, maps to a (multibit) reg -- with implicitly associated events. More often the variables and expressions in a testbench have no need for these events. E-UVM variables and expressions do not have associated events. You can instead declare explicit events when required.
In March 2015, Accellera took the UVM to IEEE for standardization. One of the stated goals of the IEEE standardization is to make UVM language agnostic. E-UVM has a port of IEEE UVM 1.0 release complete with natively supported constrained randomization and garbage collection.
SystemVerilog was designed with sole focus on RTL verification. It integrates tightly and efficiently with RTL. On the other hand Emulation and Virtual platforms generally have a C level API. Due to DPI overhead and inherent slowness, SystemVerilog becomes a bottleneck when used for testbenching these platforms.
C++ function/operator overloading and generic programming paradigm make it easy for coders to define new data types in the language. SystemVerilog, on the other hand provides first class dynamic arrays, associative arrays and implements garbage collection. These SystemVerilog features allow users to code at higher abstraction levels and to focus on the domain logic. D Programming Language brings all these strengths under one hood. E-UVM inherits these strengths from D and adds hardware modeling capabilities.
In the quest to provide fast testbenches, E-UVM does not overlook interaction with VHDL and SystemVerilog. Though E-UVM interacts as a foreign language with VHDL and SystemVerilog, it does not hinder in the functioning of the HDL simulator and makes sure that your RTL design can simulate at the best efficiency your RTL simulator provides.
E-UVM benefits from an active opensource community. Whether you need a question answered or want to contribute to open-source features, our community page will lead you in the right direction.