Enabling Multicore Testbenches

With limited on-chip RAM shared by all the processor cores, running multiple simulations on a server powered by multicore processors is no longer an optimal solution. The only way forward is to simulate using multicore enabled simulators built on shared memory software architecture.

  1. Embedded UVM is currently the only UVM implementation that enables multicore testbench simulations
  2. Embedded UVM is optimized for multicore processors with each verification IP running on a parallel thread
  3. Embedded UVM simulates the testbench on separate threads running parallel to the design simulation

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Extreme Native Performance

When you code using SystemVerilog, each integral variable and any expression that you declare, maps to a (multibit) reg -- with implicitly associated events. More often the variables and expressions in a testbench have no need for these events. E-UVM variables and expressions do not have associated events. You can instead declare explicit events when required.

  1. E-UVM code runs faster than SystemVerilog by up to 5X in addition to performance boost provided by Multicore E-UVM testbenches
  2. E-UVM testbenches compile to produce C/C++ compatible shared library modules
  3. When required, the user may optimize the testbench bottlenecks by embedding assembly code
  4. E-UVM utilizes innovative ways to integrate with Verilog/VHDL simulations, without compromising DUT simulation efficiency

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Universal Verification Methodology

In March 2015, Accellera took the UVM to IEEE for standardization. One of the stated goals of the IEEE standardization is to make UVM language agnostic. E-UVM has a port of IEEE UVM 1.0 release complete with natively supported constrained randomization and garbage collection.

  1. E-UVM implementation of UVM is a line-by-line port of the actual SystemVerilog UVM code
  2. E-UVM UVM port takes advantage of Generic Programming capabilities to take care of many UVM gotchas
  3. E-UVM adds many improvisations on top of UVM to enable system level verification and hardware/software coverification

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Hardware Software Coverification

E-UVM is built on top of D Programming Language, a mainstream systems programming language. As a result vlang is ABI compatible with C/C++ and has direct access to operating system resources.

  1. E-UVM can call C/C++ functions without any runtime overhead
  2. The constrained randomization engine in E-UVM can directly randomize variables mapped to C/C++ memory space
  3. E-UVM testbenches can access system resources directly
  4. Software drivers can directly interact with E-UVM testbenches
  5. E-UVM offers special testbenching constructs to interface with non-simulation software threads

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Emulation and Virtual Platform

SystemVerilog was designed with sole focus on RTL verification. It integrates tightly and efficiently with RTL. On the other hand Emulation and Virtual platforms generally have a C level API. Due to DPI overhead and inherent slowness, SystemVerilog becomes a bottleneck when used for testbenching these platforms.

  1. E-UVM can potentially generate transactions at multiple orders of magnitude faster compared to SystemVerilog -- thanks to native compilation and multicore abilities
  2. E-UVM offers zero integration overhead when testbenching virtual and emulation platforms -- thanks to its underlying C compatible ABI

Take a look at E-UVM/Qemu interface demo Back to Top

System Modeling Prowess

C++ function/operator overloading and generic programming paradigm make it easy for coders to define new data types in the language. SystemVerilog, on the other hand provides first class dynamic arrays, associative arrays and implements garbage collection. These SystemVerilog features allow users to code at higher abstraction levels and to focus on the domain logic. D Programming Language brings all these strengths under one hood. E-UVM inherits these strengths from D and adds hardware modeling capabilities.

  1. First class dynamic arrays and associative array data types
  2. Best in the world generic and generative programming capabilities
  3. E-UVM offers capability to model multiple asynchronous systems by letting the user create multiple simulator systems running in parallel

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Does E-UVM play along VHDL/SystemVerilog?

In the quest to provide fast testbenches, E-UVM does not overlook interaction with VHDL and SystemVerilog. Though E-UVM interacts as a foreign language with VHDL and SystemVerilog, it does not hinder in the functioning of the HDL simulator and makes sure that your RTL design can simulate at the best efficiency your RTL simulator provides.

  1. When possible, testbench simulation in E-UVM executes in parallel with RTL simulation of the design
  2. With SystemVerilog and with some Verilog simulators that support Direct Programming Interface, E-UVM integrates at the DPI layer
  3. E-UVM uses VPI interface to integrate with any Verilog simulator that does not support DPI -- but it does that without slowing down the RTL simulation
  4. E-UVM cosimulation with VHDL is supported for both VHPI and FLI interfaces
  5. E-UVM UVM based testbenches can coexist with SystemVerilog based testbenches

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Opensource Community

E-UVM benefits from an active opensource community. Whether you need a question answered or want to contribute to open-source features, our community page will lead you in the right direction.

  1. The source code is available under Boost license (with the exception of E-UVM UVM port which is released under Apache 2 license) and is publicly hosted on Github
  2. E-UVM plays along with all the opensource Verilog and VHDL simulators using DPI, VPI and VHPI interfaces

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